Copyright: Copyright 1999 Atmel Corporation.  All rights reserved.
Citation: Copyright 1999 Atmel Corporation.  All rights reserved.


STEP-BY-STEP PROCEDURE TO USE ATMEL'S AT17 SERIES EEPROM CONFIGURATOR IN XILINX'S FPGA APPLICATION
STEP-BY-STEP PROCEDURE TO USE ATMEL’S AT17 SERIES EEPROM CONFIGUATOR IN XILINX’S FPGA APPLICATION

SELECT A PROGRAMMING METHOD

DROP-IN/STAND-ALONE PROGRAMMING

       	OR

IN-SYSTEM PROGRAMMING


DROP-IN/STAND-ALONE PROGRAMMING PROCEDURE

FOUR SIMPLE STEPS TO USE AN ATMEL’S AT17 SERIES EEPROM CONFIGURATOR IN XILINX’S FPGA APPLICATION

STEP 1: SELECT AN ATMEL EEPROM TO CONFIGURE XILINX’S FPGA

STEP 2: CONSTRUCT A PROGRAMMING CIRCUIT WITH ATMEL EEPROM AND XILINX’S FPGA

STEP 3: PROGRAM AN ATMEL EEPROM WITH XILINX’S FILE USING A PROGRAMMER

STEP 4: DROP THE EEPROM INTO THE CIRCUIT AND VERIFY THE RESULTS USING A LOGIC ANALYZER

OPTIONAL CHOICES:

GO BACK TO SELECT A PROGRAMMING METHOD

DONE AND NEED MORE INFORMATION


STEP 1: SELECT AN ATMEL EEPROM TO CONFIGURE XILINX'S FPGA
 STEP 1: SELECT AN ATMEL EEPROM TO CONFIGURE XILINX’S FPGA

SELECT AN ATMEL AT17 SERIES EEPROM

SELECT AN ATMEL EEPROM PACKAGE THAT IS PIN-COMPATIBLE WITH THE XILINX PROM

       	OR

SELECT AN ATMEL EEPROM BASED ON XILINX’S FPGA CONFIGURATION BITS

OPTIONAL CHOICES:

SELECT THE NEXT STEP FOR DROP-IN/STAND-ALONE PROGRAMMING

SELECT THE NEXT STEP FOR IN-SYSTEM PROGRAMMING (ISP)


SELECT AN ATMEL EEPROM PACAKGE THAT IS PIN-COMPATIBLE WITH XILINX'S PROM
SELECT AN ATMEL EEPROM PACKAGE THAT IS PIN-COMPATIBLE WITH XILINX’S PROM

SELECT XILINX’S PROM FAMILY TO FIND OUT ATMEL’S PIN-COMPATIBLE PACKAGE

1. XILINX XC17SXXX

2. XILINX XC17SXXXA

3. XILINX XC1718XXX

4. XILINX XC1736XXX

5. XILINX XC1765XXX

6. XILINX XC17128XXX

7. XILINX XC17256XXX

8. XILINX XC17512XXX AND XC1701

OPTIONAL CHOICES:

GO BACK

SELECT THE NEXT STEP FOR DROP-IN/STAND-ALONE PROGRAMMING

SELECT THE NEXT STEP FOR IN-SYSTEM PROGRAMMING (ISP)


ATMEL'S PIN-COMPATIBLE PACKAGE WITH XILINX'S XC17SXXX SERIES PROM
ATMEL’S PIN-COMPATIBLE PACKAGE WITH XILINX’S XC17SXXX SERIES PROM

NEXT STEP

SELECT THE NEXT STEP FOR DROP-IN/STAND-ALONE PROGRAMMING

OR

SELECT THE NEXT STEP FOR IN-SYSTEM PROGRAMMING (ISP)

OPTIONAL CHOICE:

GO BACK


ATMEL'S PIN-COMPATIBLE PACKAGE WITH XILINX'S XC17SXXXA SERIES PROM
ATMEL’S PIN-COMPATIBLE PACKAGE WITH XILINX’S XC17SXXXA SERIES PROM

NEXT STEP

SELECT THE NEXT STEP FOR DROP-IN/STAND-ALONE PROGRAMMING

OR

SELECT THE NEXT STEP FOR IN-SYSTEM PROGRAMMING (ISP)

OPTIONAL CHOICE:

GO BACK


ATMEL'S PIN-COMPATIBLE PACKAGE WITH XILINX'S XC1718XXX SERIES PROM
ATMEL’S PIN-COMPATIBLE PACKAGE WITH XILINX’S XC1718XXX SERIES PROM

NEXT STEP

SELECT THE NEXT STEP FOR DROP-IN/STAND-ALONE PROGRAMMING

OR

SELECT THE NEXT STEP FOR IN-SYSTEM PROGRAMMING (ISP)

OPTIONAL CHOICE:

GO BACK


ATMEL'S PIN-COMPATIBLE PACKAGE WITH XILINX'S XC1736XXX SERIES PROM
ATMEL’S PIN-COMPATIBLE PACKAGE WITH XILINX’S XC1736XXX SERIES PROM

NEXT STEP

SELECT THE NEXT STEP FOR DROP-IN/STAND-ALONE PROGRAMMING

OR

SELECT THE NEXT STEP FOR IN-SYSTEM PROGRAMMING (ISP)

OPTIONAL CHOICE:

GO BACK


ATMEL'S PIN-COMPATIBLE PACKAGE WITH XILINX'S XC1765XXX SERIES PROM
ATMEL’S PIN-COMPATIBLE PACKAGE WITH XILINX’S XC1765XXX SERIES PROM

NEXT STEP

SELECT THE NEXT STEP FOR DROP-IN/STAND-ALONE PROGRAMMING

OR

SELECT THE NEXT STEP FOR IN-SYSTEM PROGRAMMING (ISP)

OPTIONAL CHOICE:

GO BACK


ATMEL'S PIN-COMPATIBLE PACKAGE WITH XILINX'S XC17128XXX SERIES PROM
ATMEL’S PIN-COMPATIBLE PACKAGE WITH XILINX’S XC17128XXX SERIES PROM

NEXT STEP

SELECT THE NEXT STEP FOR DROP-IN/STAND-ALONE PROGRAMMING

OR

SELECT THE NEXT STEP FOR IN-SYSTEM PROGRAMMING (ISP)

OPTIONAL CHOICE:

GO BACK


ATMEL'S PIN-COMPATIBLE PACKAGE WITH XILINX'S XC17256XXX SERIES PROM
ATMEL’S PIN-COMPATIBLE PACKAGE WITH XILINX’S XC17256XXX SERIES PROM

NEXT STEP

SELECT THE NEXT STEP FOR DROP-IN/STAND-ALONE PROGRAMMING

OR

SELECT THE NEXT STEP FOR IN-SYSTEM PROGRAMMING (ISP)

OPTIONAL CHOICE:

GO BACK


ATMEL'S PIN-COMPATIBLE PACKAGE WITH XILINX'S XC17512XXX AND XC1701 SERIES PROM
ATMEL’S PIN-COMPATIBLE PACKAGE WITH XILINX’S XC17512XXX AND XC1701 SERIES PROM

NEXT STEP

SELECT THE NEXT STEP FOR DROP-IN/STAND-ALONE PROGRAMMING

OR

SELECT THE NEXT STEP FOR IN-SYSTEM PROGRAMMING (ISP)

OPTIONAL CHOICE:

GO BACK


SELECT AN ATMEL EEPROM BASED ON XILINX'S FPGA CONFIGURATION BITS
SELECT AN ATMEL EEPROM BASED ON XILINX’S FPGA CONFIGURATION BITS

SELECT ONE OF THE FOLLOWING XILINX’S FPGA FAMILIES:

1. XILINX’S VIRTEX-II SERES FPGAS (XC2VXXX)

2. XILINX’S VIRTEX-E SERIES FPGAS (XCVXXXE)

3. XILINX’S VIRTEX SERIES FPGAS (XCVXXX)

4. XILINX’S SPARTAN-II SERIES FPGAS (XC2SXXX)

5. XILINX’S SPARTAN SERIES FPGAS (XCSXXX)

6. XILINX’S XC4000 SERIES FPGAS (XC4XXXX)

7. XILINX’S XC3000 SERIES FPGAS (XC3XXX)

NOTE: THE 20-PIN PLCC/SOIC PACKAGE OF ATMEL’S AT17 SERIES EEPROM DOES NOT HAVE THE SAME PINOUT FOR THE SAME PACAKAGE OF XILINX’S XC17V, XC17S, XC17S(A), AND 18V SERIES PROM. ALSO, THE 20-PIN SOIC PACKAGE OF ATMEL’S AT17 SERIES EEPROM DOES NOT HAVE THE SAME PINOUT AS XILINX’S XC17 SERIES PROM.

OPTIONAL CHOICES:

GO BACK

SELECT THE NEXT STEP FOR DROP-IN/STAND-ALONE PROGRAMMING

SELECT THE NEXT STEP FOR IN-SYSTEM PROGRAMMING (ISP)


XILINX'S VIRTEX-II SERIES FPGAS
XILINX’S VIRTEX-II SERIES FPGAS

SELECT THE NEXT STEP

SELECT THE NEXT STEP FOR DROP-IN/STAND-ALONE PROGRAMMING

OR

SELECT THE NEXT STEP FOR IN-SYSTEM PROGRAMMING (ISP)

OPTIONAL CHOICE:

GO BACK


XILINX'S VIRTEX-E SERIES FPGAS
XILINX’S VIRTEX-E SERIES FPGAS

  	SELECT THE NEXT STEP

SELECT THE NEXT STEP FOR DROP-IN/STAND-ALONE PROGRAMMING

OR

SELECT THE NEXT STEP FOR IN-SYSTEM PROGRAMMING (ISP)

OPTIONAL CHOICE:

GO BACK


KXILINX'S VIRTEX SERIES FPGAS
XILINX’S VIRTEX SERIES FPGAS

SELECT THE NEXT STEP

SELECT THE NEXT STEP FOR DROP-IN/STAND-ALONE PROGRAMMING

OR

SELECT THE NEXT STEP FOR IN-SYSTEM PROGRAMMING (ISP)

OPTIONAL CHOICE:

GO BACK


XILINX'S SPARTAN-II SERIES FPGAS
XILINX’S SPARTAN-II SERIES FPGAS

SELECT THE NEXT STEP:

SELECT THE NEXT STEP FOR DROP-IN/STAND-ALONE PROGRAMMING

            OR

SELECT THE NEXT STEP FOR IN-SYSTEM PROGRAMMING (ISP)

OPTIONAL CHOICE

GO BACK


XILINX'S SPARTAN SERIES FPGAS
XILINX’S SPARTAN SERIES FPGAS

SELECT THE NEXT STEP

SELECT THE NEXT STEP FOR DROP-IN/STAND-ALONE PROGRAMMING

        	OR

SELECT THE NEXT STEP FOR IN-SYSTEM PROGRAMMING (ISP)

OPTIONAL CHOICE:

GO BACK


XILINX'S XC4000 SERIES FPGAS
XILINX’S XC4000 SERIES FPGAS

SELECT THE NEXT STEP

SELECT THE NEXT STEP FOR DROP-IN/STAND-ALONE PROGRAMMING

OR

SELECT THE NEXT STEP FOR IN-SYSTEM PROGRAMMING (ISP)

OPTIONAL CHOICE:

GO BACK


XILINX'S XC3000 SERIES FPGAS
 XILINX’S XC3000 SERIES FPGAS

SELECT THE NEXT STEP

SELECT THE NEXT STEP FOR DROP-IN/STAND-ALONE PROGRAMMING

OR

SELECT THE NEXT STEP FOR IN-SYSTEM PROGRAMMING (ISP)

OPTIONAL CHOICE:

GO BACK


STEP 2: CONSTRUCT A DROP-IN/STAND-ALONE PROGRAMMING CIRCUIT WITH ATMEL'S AT17 SERIES EEPROM AND XILINX'S FPGA
STEP 2: CONSTRUCT A DROP-IN/STAND-ALONE PROGRAMMING CIRCUIT WITH ATMEL’S AT17 SERIES EEPROM AND XILINX’S FPGA

1. SOLDER THE EEPROM SOCKET TO THE TARGET BOARD BASE ON THE PINOUT OF THE EEPPROM:

ATMEL’S EEPROM PACKAGE PINOUT TABLE

2. EEPROM SOCKET CONNECTION TO XILINX’S FPGA:

DROP-IN/STAND-ALONE PROGRAMMING CIRCUIT DIAGRAM FOR SINGLE ATMEL EEPROM IN XILINX’S FPGA APPLICATION

           OR

DROP-IN/STAND-ALONE PROGRAMMING CIRCUIT DIAGRAM FOR MULTIPLE ATMEL EEPROMS IN XILINX’S FPGA APPLICATION

OPTIONAL CHOICE:

SELECT THE NEXT STEP FOR DROP-IN/STAND-ALONE PROGRAMMING


ATMEL'S EEPROM PACKAGE PINOUT TABLE
ATMEL’S EEPROM PACKAGE PINOUT TABLE

NOTE:

1. THE 20-PIN PLCC/SOIC PACKGE OF ATMEL’S AT17 SERIES EEPROM DOES NOT HAVE THE SAME PINOUT FOR THE SAME PACKAGE OF XILINX’S XC17V, XC17S, XC17S(A), AND 18V SERIES PROM.

2. THE 20-PIN SOIC PACAKGE OF ATMEL’S AT17 SERIES EEPROM DOES NOT HAVE THE   SAME PIN-OUT FOR THE SAME PACKAGE OF XILINX’S XC17 SERIES PROM.

           	GO BACK TO SELECT DROP-IN PROGRAMMING CIRCUIT DIAGRAM

OR

GO BACK TO SELECT IN-SYSTEM PROGRAMMING CIRCUIT DIAGRAM

OPTIONAL CHOICES:

SELECT THE NEXT STEP FOR DROP-IN/STAND-ALONE PROGRAMING

SELECT THE NEXT STEP FOR IN-SYSTEM PROGRAMING


DROP-IN/STAND-ALONE PROGRAMMING CIRCUIT DIAGRAM FOR SINGLE ATMEL EEPROM IN XILINX'S FPGA APPLICATION
DROP-IN/STAND-ALONE PROGRAMMING CIRCUIT DIAGRAM FOR SINGLE ATMEL’S EEPROM IN XILINX’S FPGA APPLICATION

ATMEL’S AT17C/LVXXX EEPROM in Xilinx’s Virtex-II, Virtex-E, Virtex, Spartan-II, Spartan, XC4000, and XC3000 FPGA Application

(Master Serial Mode)

NEXT STEP

PLEASE CLICK HERE TO SEE THE EXPLANATION FOR THE DROP-IN/STAND-ALONE PROGRAMMING CIRCUIT DIAGRAM

OPTIONAL CHOICES:

SELECT THE NEXT STEP FOR DROP-IN/STAND-ALONE PROGRAMING

GO BACK


DROP-IN/STAND-ALONE PROGRAMMING CIRCUIT DIAGRAM FOR MULTIPLE ATMEL EEPROMS IN XILINX'S FPGA APPLICAITON
DROP-IN/STAND-ALONE PROGRAMMING CIRCUIT DIAGRAM FOR MULTIPLE ATMEL’S EEPROMS IN XILINX’S FPGA APPLICATION

Atmel’s AT17C/LVXXX EEPROM in Xilinx’s Virtex-II, Virtex-E, Virtex, Spartan-II, Spartan, XC4000, and XC3000 FPGA Application

(Master Serial Mode)

NEXT STEP:

PLEASE CLICK HERE TO SEE THE EXPLANATION FOR DROP-IN/STAND-ALONE PROGRAMMING CIRCUIT DIAGRAM

OPTIONAL CHOICES:

SELECT THE NEXT STEP FOR DROP-IN/STAND-ALONE PROGRAMING

GO BACK


EXPLANATION OF DROP-IN/STAND-ALONE PROGRAMMING CIRCUIT DIAGRAM

Atmel’s high-density EEPROM (AT17C/LV512/010/002/040/080) will output a LOW signal from the READY pin when the device has not completed its power-up process.  This LOW signal will hold the FPGA in reset because it is connected to the *PROGRAM (PROG_B) pin of the Xilinx’s device.  The READY pin of the EEPROM is optional because it is used to prevent the race condition such as the case that the FPGA is ready, but the EEPROM has not completed its power-up process. After the power-up process is completed, the READY pin will be tri-stated.  Therefore, it requires an external pull-up resistor.   Please notice that the *PROGRAM (PROG_B) pin of Xilinx’s FPGA has an internal pull-up resistor.  Also, the AT17C/LV65/128/256 EEPROMs do not have the READY pin.

The /SER_EN pin of the EEPROM is connected to VCC.   When the /SER_EN pin is High, the configuration mode of the EEPROM will be turned on.   Since the *PROGRAM (PROG_B) pin has internal pull-up resistor, as soon as the power up process of both devices completed, Xilinx’s FPGA will start configuration by sending out signals to the EEPROM as shown in diagram of Step 4.

For drop-in/stand-alone programming of cascaded EEPROMs in the configuration mode (/SER_EN = High), the /CEO pin of the first EEPROM will output a high signal to disable the /CE pin of the second EERPOM when it has not finished loading data to Xilinx’s FPGA. After the data configuration of the first EEPROM is completed, its /CEO pin will output a low signal to activate the /CE pin of the second EEPROM. Once the /CE pin is low, the second EEPROM will start configuration.

NEXT STEP

SELECT THE NEXT STEP FOR DROP-IN/STAND-ALONE PROGRAMING

OPTIONAL CHOICES:

GO BACK TO DROP-IN/STAND-ALONE PROGRAMMING CIRCUIT DIAGRAM FOR SINGLE ATMEL EEPROM IN XILINX’S FPGA APPLICATION

OR

GO BACK TO DROP-IN/STAND-ALONE PROGRAMMING CIRCUIT DIAGRAM FOR MULTIPLE ATMEL EEPROMS IN XILINX’S FPGA APPLICATION


STEP 3: PROGRAMMING AN ATMEL EEPROM WITH XILINX'S FILE USING A PROGRAMMER
STEP 3: PROGRAMMING AN ATMEL EEPROM WITH XILINX’S FILE USING A PROGRAMMER

SELECT A PROGRAMMER TO PROGRAM ATMEL’S AT17 SERIES EEPROM

ATMEL’S PROGRAMMER

OR

OTHER THIRD-PARTY PROGRAMMERS

NOTE: ATMEL’S AT17 SERIES EEPROMS ARE SUPPORTED BY MORE THAN 50 INDUSTRIAL PROGRAMMERS.

OPTIONAL CHOICES:

SELECT THE NEXT STEP FOR DROP-IN/STAND-ALONE PROGRAMMING

SELECT THE NEXT STEP FOR IN-SYSTEM PROGRAMMING (ISP)


ATMEL'S PROGRAMMER
ATMEL’S PROGRAMMER

1.  HARDWARE SETTING

HARDWARE SETTING FOR DROP-IN/STAND-ALONE PROGRAMMING

OR

HARDWARE SETTING FOR IN-SYSTEM PROGRAMMING (ISP)

2.  SOFTWARE SETTING AND PROGRAMMING PROCEDURE IN CPS

SOFTWARE SETTING AND PROGRAMMING PROCEDURE IN CPS

OPTIONAL CHOICES:

GO BACK

SELECT THE NEXT STEP FOR DROP-IN/STAND-ALONE PROGRAMING

SELECT THE NEXT STEP FOR IN-SYSTEM PROGRAMMING (ISP)


HARDWARE SETTING FOR DROP-IN/STAND-ALONE PROGRAMMING

HARDWARE SETTING FOR ATDH2200E PROGRAMMER

1. Connect the 25-pin cable from the parallel port of the PC to connector P1 on the ATDH2200 programming board.

2. Connect the power supply from an AC wall outlet to the 9V DC connector.

3. Set jumper JP2 to PROGRAM. (Note: Read position is only use to verify reset polarity).

4. Set jumper JP3 to 5.0V if using an AT17CXXX device or 3.3V if using an AT17LVXXX device.

5. Insert AT17CXXX or AT17LVXXX device directly in the socket marked 17CXXX (U3) or via a socket adapter inserted into U3.  (Make sure the adapter is correctly placed into the socket marked 17CXXX (U3)). For an adapter that has JMP1 or/and JMP2 jumper, set the JMP1 jumper to AT17CXXX and JMP2 jumper to default unless AT17C/LV020 is used.

6. Set S1 to the "ON" position to apply power to the board.  Make sure the LED (D2) illuminates.

SOFTWARE SETTING FOR ATDH2200E PROGRAMMER

SOFTWARE SETTING AND PROGRAMMING PROCEDURE IN CPS

OPTIONAL CHOICE:

GO BACK


HARDWARE SETTING FOR IN-SYSTEM PROGRAMMING

HARDWARE SETTING

HARDWARE SETTING FOR IN-SYSTEM PROGRAMMING USING ATDH2200E

            OR

HARDWARE SETTING FOR IN-SYSTEM PROGRAMMING USING ATDH2225

SOFTWARE SETTING AND SOFTWARE SETTING IN CPS

SOFTWARE SETTING AND PROGRAMMING PROCEDURE IN CPS

OPTIONAL CHOICE:

GO BACK TO ATMEL’S PROGRAMMER


HARDWARE SETTING FOR IN-SYSTEM PROGRAMMING USING ATDH2200E

1. Connect the 25-pin cable from the parallel port of the PC to connector P1 on the ATDH2200 programming board.

2. Set jumper JP2 to PROGRAM.

3. Remove JP3 jumper and make sure the power supply is not connected from an AC wall outlet to the 9V DC connector of the ATDH2200 programming board.  The power is supplied from the ISP target board to the ATDH2200 programming board through the 10-pin ribbon cable.

4. Connect the male header of the 10-pin ribbon cable from U7 of the ATDH2200 programming board to the 10-pin ISP connector of the target board.  Note: Pin 1 of the 10-pin ribbon cable is printed in red color and pin 9 of the male header has key in it.

5. Turn on the power of the target board and make sure the LED (D2) of the ATDH2200 programming board is illuminated before starting the programming procedure.

NEXT STEP:

SOFTWARE SETTING AND PROGRAMMING PROCEDURE IN CPS

OPTIONAL CHOICE:

GO BACK


HARDWARE SETTING FOR IN-SYSTEM PROGRAMMING USING ATDH2225

1. Connect the 25-pin cable from the parallel port of the PC to connector of the ATDH2225 dongle.

2. Connect the male header of the 10-pin ribbon cable from ATDH2225 dongle to the 10-pin ISP connector of the target board.  Note: Pin 1 of the 10-pin ribbon cable is printed in red color and pin 9 of the male header has key in it.

3. Turn on the power of the target board before starting the programming procedure because the power is supply from the target board.

NEXT STEP

SOFTWARE AND PROGRAMMING PROCEDURE IN CPS

OPTIONAL CHOICE:

GO BACK


SOFTWARE SETTING AND PROGRAMMING PROCEDURE IN CPS

THE FIGURE ABOVE IS AN EXAMPLE OF PROGRAMMING AN

AT17C/LV512 EERPOM WITH A XILINX’S *.MCS FILE

PLEASE  CLICK HERE TO START THE STEP-BY-STEP PROCEDURE

OPTIONAL CHOICES:

SELECT ANOTHER PROGRAMMER

SELECT THE NEXT STEP FOR DROP-IN/STAND-ALONE PROGRAMING

SELECT THE NEXT STEP FOR IN-SYSTEM PROGRAMMING (ISP)

(NOTE:  TO PROGRAM ONE FPGA CONFIGURATION FILE FOR MULTIPLE EEPROMS THAT HAVE THE SAME DENSITY, CPS WILL INSTRUCT THE USER WHEN TO INSERT THE NEXT DEVICE AFTER THE PREVIOUS DEVICE IS PROGRAMMED).


CPS PROGRAMMING STEP ONE

SELECT THE PROGRAMMING PROCEDURE FOR XILINX’S *.MCS FILE

PROCEDURE       /E: Convert, partition, program and verify from a XILINX’S file

NEXT STEP

OPTIONAL CHOICE:

GO BACK


CPS PROGRAMMING STEP TWO

SPECIFY THE INPUT FILE DIRECTORY AND THE FILE NAME

<DRIVE>:/ [<DIRECTORY_NAME>/] <FILE_NAME>.MCS

NEXT STEP

OPTIONAL CHOICES:

GO BACK

            NOTE:

EXAMPLE: INPUT:       C:/EEPROM/DIVIDE2.MCS


CPS PROGRAMMING STEP THREE

SPECIFY THE OUTPUT FILE DIRECTORY AND THE FILE NAME

<DRIVE>:/ [DIRECTORY_NAME>/] <FILE_NAME>.BST

NEXT STEP

OPTIONAL CHOICE:

GO BACK

NOTE:

EXAMPLE:

INPUT:         C:/EEPROM/DIVIDE2.BST


CPS PROGRAMMING STEP FOUR

SELECT THE EEPROM DENSITY DEPENDS ON THE DEVICE LABEL

EEPROM DENSITY:   65K or 128K or 256K or 512K or 010M or 2M(MCM-020)

                                    or 2M(Mono-002)

NEXT STEP

OPTIONAL CHOICE:

GO BACK

NOTE:

EEPROM DENSITY:   65K       	(AT17C65 or AT17LV65)

EEPROM DENSITY:   128K     	(AT17C128 or AT17Lv128)

EEPROM DENSITY:   256K 	(AT17C256 or AT17LV256)

EEPROM DENSITY:   512K	(AT17C512 or AT17LV512)

EEPROM DENSITY:   010M	(AT17C010 or AT17LV010)

EEPROM DENSITY:   020M	(AT17020 or AT17LV020)

EEPROM DENSITY:   002M	(AT17C002 or AT17LV002)


CPS PROGRAMMING STEP FIVE

SELECT LOW FOR THE RESET POLARITY

Reset Polarity:   Low

NEXT STEP

OPTIONAL CHOICE:

GO BACK

NOTE:

THE RESET POLARITY SETTING DEPENDS ON THE FPGA APPLICATION.

SINCE MOST XILINX’S FPGA USE RESET LOW AND OE HIGH (*RESET/OE),

YOU SHOULD SET RESET POLARITY TO BE LOW IN CPS SOFTWARE.

RESET POLARITY:  LOW        (*RESET/OE)

RESET POLARITY:  HIGH        (RESET/*OE)


CPS PROGRAMMING STEP SIX
CPS PRGRAMMING STEP SIX

SELECT LPT1 FOR COMM PORT

COMM: LPT1

NEXT STEP

OPTIONAL CHOICE:

GO BACK

NOTE: LPT1 IS USED FOR THE PARALLEL PORT SETTING


CPS PROGRAMMING STEP SEVEN

SELECT FAST FOR THE DATA RATE

Data Rate:  Fast

NEXT STEP

OPTIONAL CHOICE:

GO BACK

NOTE: DATA RATE IS THE SPEED FOR PROGRAMMING THE EEPROM

             IF YOU ARE EXPERIENCING NOISE DURING PROGRAMMING,

USING A SLOWER DATA RATE MAY HELP.


CPS PROGRAMMING STEP EIGHT
CPS PROGRAMING STEP EIGHT

SET THE A2 BIT LEVEL TO LOW FOR PROGRAMMING ALL AT17 SERIES EEPROMS EXCEPT THE AT17C/LV020 EEPROM.

A2 Bit Level:    LOW

(A2 BIT LEVEL = HIGH FOR PROGRAMMING THE AT17C/LV020 EEPROM.  ALSO, FOR IN-SYSTEM PROGRAMMING, A2 BIT LEVEL MUST SET TO HIGH IF A2 PIN OF THE EEPROM IS CONNECTED TO A PULL-UP RESISTOR.)

NEXT STEP

OPTIONAL CHOICE:

GO BACK

NOTE:

THE A2 BIT IS THE DEVICE ADDRESS BIT IN THE SOFTWARE. THE A2 PIN IS THE DEVICE ADDRESS PIN IN HARDWARE.  FOR PROGRAMMING THE EEPROM, THE A2 BIT SETTING MUST BE MATCHED WITH THE A2 PIN SETTING.   IF THE A2 BIT IS SET TO LOW IN THE SOFTWARE, THE A2 PIN MUST HAVE A PULL-DOWN RESISTOR (LOW). ON THE OTHER HAND, IF A2 BIT IS SET TO HIGH IN THE SOFWARE, A2 PIN MUST HAVE A PULL-UP RESISTOR (HIGH).

WHEN USING THE ATDH2222 ADAPTER, THE JMP2 JUMPER SETTING TO DEFAULT POSITION IS ACTUALLY CONNECTING THE A2 PIN TO A PULL-DOWN RESISTOR.  THE JMP2 JUMPER SETTING TO 2 MEG IS CONNECTING THE A2 PIN TO A PULL-UP RESISTOR.

ALSO, THE A2 PIN HAS AN INTERNAL PULL-DOWN CIRCUITRY FOR ALL NEW VERSIONS OF THE AT17C/LV65/128/256 AND THE OLD VERSIONS OF AT17C/LV512/010/002 EEPROMS.  THEREFORE, SETTING THE A2 BIT LEVEL TO LOW CAN PROGRAM THE DEVICE IF THE A2 PIN IS FLOATING OR CONNECTED TO AN EXTERNAL PULL-DOWN RESISTOR.


CPS PROGRAMMING STEP NINE

CLICK ON “Start Procedure” TO START PROGRAMMING THE EEPROM.

NEXT STEP

OPTIONAL CHOICE:

GO BACK


CPS PROGRAMMING STEP TEN

CLICK ON “View Log File” TO CHECK THE DETAILS OF THE PROGRAMMING RESULTS

NEXT STEP

SELECT THE NEXT STEP FOR DROP-IN/STAND-ALONE PROGRAMMING

OR

SELECT THE NEXT STEP FOR IN-SYSTEM PROGRAMMING (ISP)

OPTIONAL CHOICE:

GO BACK


THIRD-PARTY PROGRAMMERS

FIVE MAJOR STEPS TO PERFORM DROP-IN/STAND-ALONE PROGRAMMING OF ATMEL’S AT17 SERIES EEPROM USING A THIRD PARTY PROGRAMMER ARE DESCRIBED BELOW:

STEP 1:  PLACE THE EEPROM INTO THE APPROPRIATE

    SOCKET/ADAPTER.

STEP 2:  SELECT THE CORRECT DENSITY LABEL AND PACKAGE TYPE OF

ATMEL’S AT17 SERIES EEPROMS FROM THE PROGRAMMING SOFTWARE.

STEP 3.  LOAD THE PROGRAMMING FILE WITH THE CORRECT FORMAT

SETTING TO THE DATA BUFFER OF THE THIRD-PARTY

PROGRAMMER.

STEP 4.  SET THE RESET POLARITY LEVEL ACCORDING TO THE

 	    APPLICATION OF THE DEVICE (LOW FOR XILINX’S FPGA).

STEP 5.  PROGRAM THE DEVICE.

NOTE:  MOST OF THE THIRD-PARTY PROGRAMMERS DO NOT SUPPORT IN-SYSTEM PROGRAMMING.  THE DETAIL ABOUT THE THRID-PARTY PROGRAMMER SUPPORT STATUS AND CONTACT INFORMATION CAN BE OBTAINED FROM ATMEL’S WEB SITE AT http://www.atmel.com/atmel/acrobat/doc0585.pdf

NEXT STEP

SELECT THE NEXT STEP FOR DROP-IN/STAND-ALONE PROGRAMING

OR

SELECT THE NEXT STEP FOR IN-SYSTEM PROGRAMMING (ISP)

OPTIONAL CHOICE:

GO BACK


 STEP 4: VERIFY THE CONFIGURATION RESULTS USING A LOGIC ANALYZER

MONITORING THE SIGNALS DURING CONFIGURATION WILL SHOW

THE STATUS OF THE FPGA CONFIGURATION FROM THE EEPROM

The following signals should be monitored using a logic analyzer:

      	XILINX’S FPGA	             ATMEL’S EEPROM

CCLK                	  CONNECTED TO  	CLK

DIN (D0)       	 	  CONNECTED TO  	DATA

*INIT                 	  CONNECTED TO  	*RESET/OE

DONE     	  CONNECTED TO  	*CE

THE GROUND LEAD OF THE LOGIC ANALYZER MUST BE GROUND.

Sampling frequency (Fs) = 2 x Configuration frequency (fcclk)

If fcclk = 1 MHz (100 ns), sampling frequency(Fs) = 2 x 1 MHZ = 2 MHZ (200 ns).

            The typical range of the sampling frequency is from 200 ns to 500 ms.

Setting the trigger level of the logic analyzer at the rising edge of the *INIT line and then adjusting the sampling frequency with continued running will display the complete waveform during configuration as shown above.

Please notice that *INIT pin from XILINX’S FPGA is connecting to the *RESET/OE pin of the EEPROM.  When the *INIT pin of the FPGA sends out a High signal to the OE (Output Enable) pin of the EEPROM, the configuration data will be clocking out of the EEPROM.  The DONE pin of the FPGA will be low during configuration and will be pull-up to high to disable the /CE pin of the EEPROM.  When this pin goes from low to high, it indicates that configuration is successfully done.

DONE AND NEED MORE INFORMATION

OPTIONAL CHIOCES:

GO BACK TO SELECT A PROGRAMMING METHOD

GO BACK TO THE DROP-IN/STAND-ALONE PROGRAMMING PROCEDURE

GO BACK TO THE IN-SYSTEM PROGRAMMING PROCEDURE


 IN-SYSTEM PROGRAMMING PROCEDURE

FOUR SIMPLE STEPS TO USE ATMEL’S AT17 SERIES EEPROM IN XILINX’S FPGA APPLICATION

STEP 1: SELECT AN ATMEL EEPROM TO CONFIGURE XILINX’S FPGA

STEP 2: CONSTRUCT AN ISP PROGRAMMING CIRCUIT WITH ATMEL EEPROM AND XILINX’S FPGA

STEP 3: PROGRAM AN ATMEL EEPROM WITH XILINX’S FILE USING A PROGRAMMER

STEP 4: RELEASE THE ISP CABLE AND VERIFY THE CONFIGURATION RESULT USING A LOGIC ANALYZER

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STEP 2: CONSTRUCT AN IN-SYSTEM PROGRAMMING CIRCUIT WITH ATMEL'S AT17 SERIES EEPROM AND XILINX'S FPGA
STEP 2: CONSTRUCT AN IN-SYSTEM PROGRAMMING CIRCUIT WITH ATMEL’S EEPROM AND XILINX’S FPGA

1. SOLDER THE EEPROM TO THE TARGET BOARD BASE ON THE PIN-OUT OF THE EEPPROM:

ATMEL’S EEPROM PACKAGE PINOUT TABLE

2. EEPROM SOCKET CONNECTION TO XILINX’S FPGA:

IN-SYSTEM PROGRAMMING CIRCUIT DIAGRAM FOR SINGLE ATMEL EEPROM IN XILINX’S FPGA APPLICATION

           OR

IN-SYSTEM PROGRAMMING CIRCUIT DIAGRAM FOR MULTIPLE ATMEL EEPROMS IN XILINX’S FPGA APPLICATION

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IN-SYSTEM PROGRAMMING CIRCUIT DIAGRAM FOR SINGLE ATMEL EEPROM IN XILINX'S FPGA APPLICATION
IN-SYSTEM PROGRAMMING CIRCUIT DIAGRAM FOR SINGLE ATMEL’S EEPROM IN XILINX’S FPGA APPLICATION

Atmel’s AT17C/LVXXX EEPROM in Xilinx’s Virtex-II, Virtex-E, Virtex, Spartan-II, Spartan, XC4000, and XC3000 FPGA Application

(Master Serial Mode)

THE AT17C/LV65, AT17C/LV128, AND THE AT17C/LV256 EEPROMS THAT ARE USED IN THIS ISP CIRCUIT MUST HAVE A “B” OR  AN “ES” LABEL WRITTEN ON THE DATE CODE (SUCH AS 0050B OR 0050ES).  ONLY THE 8-PIN SOIC PACKAGE IS AN EXCEPTION. OTHERWISE AN EXTRA MULTIPLEXER MUST BE USED FOR THIS ISP CIRCUIT.

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IN-SYSTEM PROGRAMMING CIRCUIT DIAGRAM FOR MULTIPLE ATMEL EEPROMS IN XILINX'S FPGA APPLICATION
IN-SYSTEM PROGRAMMING CIRCUIT DIAGRAM FOR MULTIPLE ATMEL’S EEPROMS IN XILINX’S FPGA APPLICATION

Atmel’s AT17C/LVXXX EEPROM in Xilinx’s Virtex-II, Virtex-E, Virtex, Spartan-II, Spartan, XC4000, and XC3000 FPGA Application

(Master Serial Mode)

THE AT17C/LV65, AT17C/LV128, AND THE AT17C/LV256 EEPROMS THAT ARE USED IN THIS ISP CIRCUIT MUST HAVE A “B” OR AN “ES” LABEL WRITTEN ON THE DATE CODE (SUCH AS 0050B OR 0050ES).  ONLY THE 8-PIN SOIC PACKAGE IS AN EXCEPTION.  OTHERWISE AN EXTRA MULTIPLEXER MUST BE USED FOR THIS ISP CIRCUIT.

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EXPLANATION OF IN-SYSTEM PROGRAMMING CIRCUIT DIAGRAM

Atmel’s high density EEPROM (AT17C/LV512/010/002/040/080) will output a LOW signal from the READY pin when the device has not completed its power up process.  This LOW signal will hold the FPGA in reset since it is connected to the *PROGRAM (PROG_B) pin of the Xilinx’s device.  The READY pin of the EEPROM is optional because it is used to prevent the race condition such as the case that the FPGA is ready, but the EEPROM has not completed its power up process. After the power up process is completed, the READY pin will be tri-stated.  Therefore, it requires an external pull-up resistor.   Please notice that the *PROGRAM (PROG_B) pin of Xilinx’s FPGA has internal pull-up resistor.  Also, the AT17C/LV65/128/256 EEPROMs do not have the READY pin. If the READY pin is not used, the diode can be eliminated.

When the 10-pin ribbon cable from the ATDH2200 programming board or ATDH2225 ISP direct download cable is connected to the 10-pin ISP male connector, the /SER_EN line will be LOW because pin #10 is connected to Ground (GND) on the other side of the ATDH2200 programmer or the ATDH2222 adapter. This LOW signal will also hold the *PROGRAM (PROG_B) pin of the FPGA in reset.  When the /SER_EN pin is LOW, the programming mode of the EEPROM will be turned on.  The configuration data will be programmed from the PC to the EEPROM through ATDH2200 programming board or ATDH2225 ISP direct download cable and the 10-ribbon cable.  After the data is programmed to the EEPROM, the 10-pin ribbon cable should be released from the ISP connector in order to allow the pull-up resistor to turn the /SER_EN line to HIGH.  When the /SER_EN pin is High, the configuration mode of the EEPROM will be turned on.   As soon as the 10-pin ribbon cable is released, the internal pull-up resistor of the *PROGRAM (PROG_B) pin will also be active. When this pin is active High, Xilinx’s FPGA will start configuration by sending out signals as shown in figure of Step 4.

The diode in the ISP circuit is used to prevent the READY pin or the external control of the *PROGRAM (PROG_B) pin to toggle the /SER_EN pin of the EEPROM to be low when the power up process has not completed.

For In-system programming of cascaded EEPROMs in the configuration mode (/SER_EN = High), the /CEO pin of the first EEPROM will output a high signal to disable the /CE pin of the second EERPOM when it has not finished loading data to Xilinx’s FPGA. After the data configuration of the first EEPROM is completed, its /CEO pin will output a low signal to activate the /CE pin of the second EEPROM. Once the /CE pin is low, the second EEPROM will start configuration.

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INFORMATION

THANK YOU FOR YOUR INTEREST IN USING ATMEL’S DEVICES.

PLEASE CONTACT ATMEL’S CONFIGURATOR TECHNICAL SUPPORT TEAM IF YOU HAVE ANY QUESTIONS ABOUT ATMEL’S FPGA CONFIGURATION MEMORIES (AT17C/LVXXX EEPROMs).

Atmel’s Configurator Technical Support Team:

Phone: 1-408-436-4119     (San Jose,  U.S.A.)

Email:   configurator@atmel.com

Frequently Asked Questions:

http://www.atmel.com/atmel/faqs/cgi/search_records.cgi?FAQ_Grouping_1=FPGA+Configuration+Memory

Datasheet:

http://www.atmel.com/atmel/products/prod182.htm

Application Notes:

http://www.atmel.com/atmel/products/prod183.htm

Third-party programmer support status:

http://www.atmel.com/atmel/acrobat/doc0585.pdf

Where to order parts:

http://www.atmel.com/atmel/contacts/

Sample request:

http://www.atmel.com/atmel/samples/

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